Hitachi HIDIC EH-150 Applications Manual page 77

Programable controller; ethernet module(eh-eth)
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Module Status Register (MDSR)
Bit
15
14
-
-
+0
Bit 15-8: Reserved
These bits are reserved bits. Usually "0" are set.
Bit 7: Fatal error bit (FAE)
This bit shows that fatal error occurs in the firmware of this module (TCP/IP, UDP/IP protocol). In case that this
bit is "1" The reset operation is required with this module. (by reset button or FUN201)
Bit7: FAE
0
There is no error.
1
There is fatal error in this module.
Bit 6: Operation mode bit (OPM)
The status of DIP-switch 1 is reflected on this bit.
Bit6: OPM
0
Normal operation mode
1
Ethernet information configuration (set-up) mode.
Bit 5: SUM Error bit (SME)
The result of the sum check for FLASH memory which stores system program (Firmware).
Bit5: SME
0
There is no error.
1
The sum error is detected. (FLASH memory may be damaged.)
Bit 4: Ethernet information configuration error bit (EIE)
Illegal Ethernet information is set. In the case of this bit set "1", I.ERR LED turns on.
Bit4: EIE
0
There is no error.
1
The illegal Ethernet information configuration (set-up) is detected.
Bit 3: Existence response bit (AVR)
The result of general working check for EH-ETH. The data (IAV bit of control register) will be reflected here.
Bit3: AVR
0
The data set in Existence confirmation Request bit (IAV) of Control area are reflected.
1
Bit 2: Automatic Sending/Receiving enable bit (ATR)
This bit shows the current specified status of Automatic Sending/Receiving function is disable or enable.
Bit2: ATR
0
Automatic Sending/Receiving function is disable.
1
Automatic Sending/Receiving function is enable.
Bit 1: I.ERR LED lighting condition bit (IERR)
This bit shows the current condition of I.ERR LED.
Bit1: IERR
0
I.ERR LED is turned off.
1
I.ERR LED is turned on.
Bit 0: ERR LED lighting condition bit (ERR)
This bit show the current condition of ERR LED.
Bit0: ERR
0
ERR LED is turned off.
1
ERR LED is turned on.
13
12
11
10
9
-
-
-
-
-
8-2
Chapter 8 Register Structure
8
7
6
5
4
-
FAE OPM SME
EIE AVR ATR IERR ERR
Description
Description
Description
Description
Description
Description
Description
Description
3
2
1
0

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