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TYPICAL PERFORMANCE
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
Typical performance applies only to the configuration as shipped. The MC145220EVK is shipped with
V+ = 5 V. For lowest phase noise in single or dual loop mode, a 50 Ω load must be connected to J12.
Supply Voltage (J8)
Supply Current (J8) (Note 1)
Available Current (Note 2)
Frequency Range (Note 3)
Reference Frequency (M1)
Temperature Stability
(M1, – 30 C to + 70 C)
Reference Frequency (M5)
Temperature Stability
(M5, – 30 C to + 85 C)
TCXO Aging (M1, M5)
Step Size
Power Output
Frequency Accuracy
Reference Sidebands (Note 4)
Phase Noise (100 Hz)
Phase Noise (10 kHz) (Note 5)
Switching Time (Note 6)
NOTES:
1. Supply current is current the board requires without user modifications.
2. Available current is the sum of currents available to the user (in the prototype area) from the 5 V and 8.5 V supply. The 12 V supply is not
regulated. Current at 12 V is limited by the external power supply. If the on–board VCO and amplifier are disconnected from the power bus,
more current can be drawn in the prototype area. The current flowing into U5 (the 8.5 V regulator) should not exceed 180 mA. This will limit
temperature rise in U5.
3. Frequency ranges require use of the 5 V default charge pump supply voltage.
4. VCO sidebands on PLL at low step sizes (10 kHz) are limited by control line leakage of the VCO. Up to 24 nA of leakage has been seen.
At higher step sizes (100 kHz and above), this effect is much less noticable. This did not affect PLL because its VCO leakage was less than
10 pA.
5. 10 kHz phase noise is limited by the PLL device noise. For low noise designs, the loop bandwidth is made narrower and the VCO is relied
upon to provide the 10 kHz phase noise. This can be seen on the EVKs since the VCOs have much lower noise.
6. 10 MHz step, within
Due to the software architecture, when the user is measuring the switching time of a single board in dual loop mode, it takes 20 ms to load
the data as compared to single loop mode, which takes 8 ms to load the data. This is a limitation of the software, not the IC.
To find the actual PLL switching time, subtract 8 or 20 ms from the switching time stated in the table.
MOTOROLA
Freescale Semiconductor, Inc.
1 kHz of final frequency ('220).
For More Information On This Product,
Go to: www.freescale.com
Single Loop PLL Single Loop PLL
11.5 – 12.5 V
733 – 743 MHz
790 – 820 MHz
10.01 MHz
<
14.4 MHz
<
2 ppm
<
10 kHz
– 3.0 dBm
1.5 kHz
– 57 dB
– 65 dBc/Hz
– 56 dBc/Hz
– 104 dBc/Hz
– 90 dBc/Hz
24 ms
Dual Loop PLL
177 mA
45 mA
60 – 80 MHz
2.5 ppm
N/A
N/A
1 ppm / year
10 Hz
– 5.0 dBm
4.5 – 7.5 dBm
1.5 kHz
50 Hz
– 74 dB
– 57 dB
– 50 dBc/Hz
– 89 dBc/Hz
40 ms
45 ms
MC145220EVK
7
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