Panasonic BB-HCM381A Service Manual page 82

- The CPU is a 32-bit RISC CPU and performs mainly hardware control,
TCP/IP protocol processing and applications such as http and FTP.
- The clock setting is 65.536MHz, which is the four times of 16.384MHz
oscillation in the X101 by PLL.
- There are two types of external bus: the General-purpose bus through
SRAM I/F and the bus for SDRAM only.
- The General-purpose bus is connected to a Flash Memory for program
storage.
- The capacity of the Flash Memory (IC101) is 32Mbit (2Mx16bit); the
program, the setting information for the network camera and the MAC
address are stored.
- The SDRAM (IC105) is 64Mbit (4Mx16bit) and used for the CPU
processing work, the communication data storage and the sound and
image data storage.
- The RESET IC (IC106) monitors the power supply voltage, detects the
rising edge of +3.3V and generates the Hardware ResetSignal.
- The IC302 is a RTC (Real Time Clock) and is used for the time setting of
the image transfer. It is backed up at power-off by a lithium battery
(BAT501). The I/F with the CPU has a dedicated controller. (5-line I/F)
- The Encryption block inside the IC103 is an IPsec communication
encryption engine and is used at the software protocol processing.
- The camera CPU (IC902) on video board is connected to the CPU (IC103)
through serial interface.
Signal Flow
1. When a request from the PC is received through LAN, the CGI
command is analyzed at the CPU and the requestedimage/sound data
are generated.
2. The JPEG image and sound data accumulated on the SDRAM are
formed in IP packet by the protocol processing.
3. If the IPsec is not encrypted, it is sent without change. If it is encrypted,
this is carried out in the Encryption Block and a header is added to
send to the Ethernet MAC part.
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