Spi_Mosi (Master Out, Slave In); Ispi Programming Model - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

12.3.2 SPI_MOSI (Master Out, Slave In)

In slave mode, this pin is the input to the shift register. A new bit is shifted in on each
leading edge of SPI_CLK in normal clock mode or on each trailing edge of SPI_CLK
in inverted clock mode. In either master mode, this pin is the output of the shift regis-
ter. A new data bit is presented on each falling edge of the SPI_CLK in normal clock
mode (PHA=0, POL=0).
12.3.3 SPI_EN
In manual mode, this pin is directly controlled by the SPI_EN bit in the ISPI control
register (bit 12), and can be used as a general-purpose output as well as for enabling
an external device. In interval mode, its control is gated by the state machine. As an
input (in slave mode), SPI_EN is active low. As an output (in master modes), the
active sense is determined by the value of bit SNS in the ISPI control register.
12.3.4 SPI_CLK
This pin is the clock output in manual or interval mode. When the ISPI is enabled, a
selectable number of clock pulses are issued.
In slave mode, this pin is an input but controls SPI operation just as it does in the two
master modes. In slave mode, SPI_CLK must not exceed HI_REFCLK/16.
12.3.5 SPI_GP
This output pin is a general-purpose output which can be used as a control signal to a
selected external device. The value driven out is controlled by the SPIGP bit in the
ISPI control register.

12.4 ISPI Programming Model

These registers control the operation of the ISPI and report its status. The data regis-
ter exchanges data with external slave devices. After reset, all bits are cleared.
These registers should be accessed with halfword accesses. Accesses other than
halfword in size result in undefined activity.
Address
10008000
10008002
10008004
10008006
10008008
to
10008FFF
MOTOROLA
12-4
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Table 12-1 ISPI Module Address Map
Use
ISPI Send/Receive Data Register (SPDR)
ISPI Control Register (SPCR)
ISPI Interval Control Register (SPICR)
ISPI Status Register (SPSR)
Reserved
INTERVAL MODE SERIAL PERIPHERAL INTERFACE
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