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SQA — Sequential Breakpoint A Arm Occurrence
This read-only status bit is set when sequential operation is enabled and a memory
breakpoint A event has occurred to enable memory breakpoint B operation. This bit is
cleared on test logic reset or when debug mode is exited with the GO and EX bits set.
PM — Processor Mode
These status bits indicate the processor operating mode. They allow coordination of
the OnCE controller with the CPU to synchronize the two.
C.10.4 Memory Address Latch (MAL)
The memory address latch (MAL) is a 32-bit register that latches the address bus on
every access.
C.10.5 Breakpoint Address Base Registers (BABA, BABB)
The 32-bit breakpoint address base registers (BABA, BABB) store memory break-
point base addresses. BABA and BABB can be read or written through the OnCE
serial interface. Before enabling breakpoints, the external command controller should
load these registers.
C.10.6 Breakpoint Address Mask Registers (BAMA, BAMB)
The 32-bit breakpoint address mask registers (BAMA, BAMB) store memory break-
point base address masks. BAMA and BAMB can be read or written through the
OnCE serial interface. Before enabling breakpoints, the external command controller
should load these registers.
C.10.7 Breakpoint Address Comparators
Each breakpoint address comparator compares the current memory address (stored
in MAL) with the contents of the base, as appropriately masked by the BAMx. When a
match occurs, the comparator signals the breakpoint logic.
C.10.8 Memory Breakpoint Counters (MBCA, MBCB)
The 16-bit memory breakpoint counter x (MBCx) register is loaded with a value equal
to the number of times, minus one, that a memory access event can occur before a
memory breakpoint is declared.
C.10.9 Program Counter Register (PC)
The program counter register (PC) is a 32-bit latch that stores the value of the pro-
gram counter that was present when the chip entered debug mode.
MMC2001
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
Table C-23 Processor Mode Field Definition
PM[1:0]
00
Processor in normal mode
01
Processor in stop, doze, or wait mode
10
Processor in debug mode
11
Reserved
PROGRAMMING REFERENCE
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Meaning
MOTOROLA
C-51
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