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DRV — Drive Type
This bit controls the configuration of the SPI_CLK, SPI_EN and SPI_MOSI output
buffers in either master mode of the ISPI (MSTR=1). In slave mode, this bit is ignored.
0 = Outputs are totem-pole while in either master mode
1 = Outputs are open-drain while in either master mode
MSTR — Master Mode
This bit controls the mode of the ISPI. In slave mode, the SPI_CLK and SPI_EN pins
are inputs; in master modes, they are outputs.
0 = ISPI operates in slave mode
1 = ISPI operates in either interval mode or manual mode (see IVL_EN in SICR)
IRQ_EN — Interrupt Request Enable
This bit enables/disables the ISPI interrupt request output signal. This bit is cleared to
zero on reset.
0 = Interrupts disabled
1 = Interrupts enabled
PHA — Phase
This bit controls the phase shift of the SPI_CLK.
0 = Normal phase
1 = Shift advance to opposite phase
POL — Polarity
This bit controls the polarity of the SPI_CLK.
0 = Normal polarity
1 = Inverted polarity
SPIGP — SPI_GP Control
This bit controls the data on the SPI_GP pin.
0 = Pin driven low
1 = Pin driven high
BAUD RATE
These bits select the baud rate of the ISPI bit clock based on divisions of the system
clock. The master clock for the ISPI is HI_REFCLK.
MOTOROLA
C-32
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
Table C-15 BAUD RATE Values
Value
000
001
010
011
100
101
110
111
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
Divide By
8
16
32
64
128
256
512
1024
MMC2001
REFERENCE MANUAL
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