External Interrupts/Gpio (Edge Port); Overview; Interrupt/General-Purpose I/O Pin Descriptions (Int[0:7]); External Interrupt/Gpio Block Diagram - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

EXTERNAL INTERRUPTS/GPIO (EDGE PORT)

13.1 Overview

The MMC2001 has eight external interrupt pins. Each pin can be configured individu-
ally as a level-sensitive interrupt, an edge-detecting interrupt (rising edge, falling
edge, or both), or a general-purpose I/O pin.
EPPAR
[2n, 2n+1]
Data
Bus
EPDR[n]
EPDDR[n]
Figure 13-1 External Interrupt/GPIO Block Diagram

13.2 Interrupt/General-Purpose I/O Pin Descriptions (INT[0:7])

When programmed as inputs, these pins use Schmitt triggered input buffers. When
edge triggered, triggering occurs at a voltage level and is not directly related to the fall
time of the interrupt signal. However, as the fall time of the interrupt signal increases,
the probability of generating multiple interrupts due to this "noise" also increases. All
default to general-purpose input pins at reset. The interrupt request function on these
pins is masked in the interrupt controller fast interrupt enable register (FIER) and nor-
mal interrupt enable register (NIER).
MMC2001
REFERENCE MANUAL
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Freescale Semiconductor, Inc.
SECTION 13
EPPAR[2n+1]
EPPAR[2n]
EPPAR[2n+1]
Falling
Edge Detect
EPPAR[2n]
Rising
Edge Detect
EXTERNAL INTERRUPTS/GPIO (EDGE PORT)
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EPFR[n]
To Interrupt
Controller
MOTOROLA
13-1