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16.11.1 Program Counter Register (PC)
The OnCE program counter register (PC) is a 32-bit latch that stores the value in the
CPU program counter when the device enters debug mode. The CPU PC is affected
by operations performed during debug mode and must be restored by the external
command controller when the CPU returns to normal mode.
16.11.2 Instruction Register (IR)
The instruction register (IR) provides a mechanism for controlling the debug session.
The IR allows the debug control block to execute selected instructions; the debug
control module provides single-step capability.
When scan-out begins, the IR contains the opcode of the next instruction to be exe-
cuted at the time debug mode was entered. This opcode must be saved in order to
resume normal execution at the point debug mode was entered.
On scan-in, the IR can be filled with an opcode selected by debug control software in
preparation for exiting debug mode. Selecting appropriate instructions allows a user
to examine or change memory locations and processor registers.
Once the debug session is complete and normal processing is to be resumed, the IR
can be loaded with the value originally scanned out.
16.11.3 Control State Register (CTL)
The control state register (CTL) is used to set control values when debug mode is
exited. On scan-in, this register is used to control specific aspects of the CPU. Certain
bits reflect internal processor status and should be restored to their original values.
The CTL is a 16-bit latch that stores the value of certain internal CPU state variables
before debug mode is entered. This register is affected by the operations performed
during the debug session and should be restored by the external command controller
when returning to normal mode. In addition to saved internal state variables, the bits
are used by emulation firmware to control the debug process.
Reserved bits represent the internal processor state. Restore these bits to their origi-
nal value after a debug session is completed, i.e., when a OnCE command is issued
with the GO and EX bits set and not ignored. Set these bits to ones while instructions
are executed during a debug session.
CTL — Control State Register
15
14
13
12
R
Reserved
W
RESET:
MOTOROLA
16-18
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Freescale Semiconductor, Inc.
11
10
9
8
FFY
0
Figure 16-10 Control State Register
OnCE™ DEBUG MODULE
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7
6
5
4
FDB
SZ
0
0
0
0
3
2
1
0
TC
Reserved
0
0
MMC2001
REFERENCE MANUAL
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