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Programming Model
31
Field
Reset
R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through the BDM
port using the
RDMREG
Descriptions."
DRc[4–0]
Figure 29-9. Program Counter Breakpoint Register (PBR)
Table 29-12 describes PBR fields.
Bits
Name
31–0
Address
PC breakpoint address. The 32-bit address to be compared with the PC as a breakpoint trigger.
Figure 29-9 shows PBMR.
31
Field
Reset
R/W Write. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG instruction and
DRc[4–0]
Figure 29-10. Program Counter Breakpoint Mask Register (PBMR)
Table 29-13 describes PBMR fields.
Bits
Name
31–0
Mask
PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to the
appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
29.4.7 Trigger Definition Register (TDR)
The TDR, shown in Table 29-11, configures the operation of the hardware breakpoint logic
that corresponds with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers
within the debug module. The TDR controls the actions taken under the defined conditions.
Breakpoint logic may be configured as a one- or two-level trigger. TDR[31–16] define the
second-level trigger and bits 15–0 define the first-level trigger.
29-14
Program Counter
and
commands using values shown in Section 29.5.3.3, "Command Set
WDMREG
Table 29-12. PBR Field Descriptions
via the BDM port using the wdmreg command.
Table 29-13. PBMR Field Descriptions
MCF5282 User's Manual
—
0x08
Description
Mask
—
0x09
Description
0
0
MOTOROLA
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