Table of Contents
Advertisement
Operation
Signal
Transmitter Serial
UTXDn is held high (mark condition) when the transmitter is disabled, idle, or operating in the local
Data Output
loop-back mode. Data is shifted out on UTXDn on the falling edge of the clock source, with the least
(UTXDn)
significant bit (lsb) sent first.
Receiver Serial
Data received on URXDn is sampled on the rising edge of the clock source, with the lsb received first.
Data Input
(URXDn)
Clear-to-
This input can generate an interrupt on a change of state.
Send (UCTSn)
Request-to-
This output can be programmed to be negated or asserted automatically by either the receiver or the
Send (URTSn)
transmitter. When connected to a transmitter's UCTSn, URTSn can control serial data flow.
Figure 23-17 shows a signal configuration for a UART/RS-232 interface.
23.5 Operation
This section describes operation of the clock source generator, transmitter, and receiver.
23.5.1 Transmitter/Receiver Clock Source
The system clock serves as the basic timing reference for the clock source generator logic,
which consists of a clock generator and a programmable 16-bit divider dedicated to each
UART. The clock generator might not produce standard baud rates if the system clock is
used, so the 16-bit divider should be used.
23.5.1.1 Programmable Divider
As Figure 23-18 shows, the UARTn transmitter and receiver can use the following clock
sources:
• An external clock signal on the DTINn pin that can be divided by 16. When not
divided, DTINn provides a synchronous clock mode; when divided by 16, it is
asynchronous.
23-18
Table 23-12. UART Module Signals
UART
URTSn
UCTSn
UTXDn
URXDn
Figure 23-17. UART/RS-232 Interface
MCF5282 User's Manual
Description
RS-232 Transceiver
DI2
DO2
DI1
DO1
MOTOROLA
Advertisement
Table of Contents
