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overview, 28-1
registers
control (RCR), 28-3
status (RSR), 28-4
requests
internal, 28-10
synchronous, 28-10
sources of reset, 28-6
external reset, 28-7
LDV reset, 28-7
loss-of-clock reset, 28-7
loss-of-lock reset, 28-7
power-on reset, 28-6
software reset, 28-7
watchdog timer reset, 28-7
status flags, 28-11
timing diagrams
RSTI and configuration override, 33-19
Reset exception, 2-16
RTE instruction, 2-16
Run mode, 7-6
Rx/Tx frames, 25-6
S
SACU
features, 8-14
overview, 8-14
SAMPLE/PRELOAD instructions, 31-9
Sampling mode (SAMP), 25-24
S-clock, 25-14
SCM
features, 8-1
low-power modes, 7-7
memory map, 8-2, 8-15
overview, 8-1
registers
bus master park (MPARK), 8-12
core reset status (CRSR), 8-6
core watchdog control (CWCR), 8-6
core watchdog service (CWSR), 8-9
grouped
peripheral
(GPACRn), 8-18
IPSBAR, 8-3
master privilege (MPR), 8-16
peripheral access control (PACRn), 8-16
RAMBAR, 2-8, 2-8, 5-2, 8-4
SACU, 8-14
features, 8-14
overview, 8-14
SDRAM controller
auto-refresh, 15-15
block diagram, 15-2
burst page mode, 15-13
definitions, 15-1
MOTOROLA
INDEX
access
control
MCF5282 User's Manual
example
DACR initialization, 15-21
DCR initialization, 15-20
DMR initialization, 15-22
initialization code, 15-24
interface configuration, 15-20
initialization, 15-17
interfacing, 15-13
memory map, 15-4
operation
general, 15-3
low-power modes, 7-8
synchronous
address multiplexing, 15-9
general guidelines, 15-9
overview, 15-1
registers
address and control 1–0 (DACRn), 15-6
control (DCR), 15-5
mask (DMRn), 15-8
mode register
initialization, 15-23
settings, 15-18
self-refresh, 15-16
timing diagrams
read cycle, 33-16
write cycle, 33-17
timing specifications, 33-16
Self-received frames, 25-10
Signals
block diagram, 14-2
bus
address bus (A23–0), 14-18
byte strobes (BS3–0), 14-19
chip select (CS6–0), 14-20
data (D31–0), 14-18
output enable (OE), 14-19
read/write (R/W), 14-19
summary, 13-1
transfer acknowledge (TA), 14-19
transfer error acknowledge (TEA), 14-19
transfer in progress (TIP), 14-20
transfer size (SIZ1–0), 14-19
transfer start (TS), 14-20
chip configuration
CLKMOD1–0, 9-5
chip configuration module
CLKMOD1–0, 14-22, 30-3
RCON, 14-22, 30-3
reset configuration override (D26–24, 21,
19–16), 30-3
chip select module
byte strobes (BS3–0), 12-1
chip select (CS6–0), 12-1
output enable (OE), 12-1
Index-13
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