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27.3 Modes of Operation
This subsection describes the two modes of operation in which the QADC does not perform
conversions in a regular fashion:
• Debug mode
• Stop mode
27.3.1 Debug Mode
The QDBG bit in the module configuration register (QADCMCR) governs behavior of the
QADC when the CPU enters background debug mode. When QDBG is clear, the QADC
operates normally and is unaffected by CPU background debug mode. See Section 27.6.1.
When QDBG is set and the CPU enters background debug mode, the QADC finishes any
conversion in progress and then freezes. This is QADC debug mode. Depending on when
debug mode is entered, the three possible queue freeze scenarios are:
• When a queue is not executing, the QADC freezes immediately.
• When a queue is executing, the QADC completes the current conversion and then
freezes.
• If during the execution of the current conversion, the queue operating mode for the
active queue is changed, or a queue 2 abort occurs, the QADC freezes immediately.
When the QADC enters debug mode while a queue is active, the current CCW location of
the queue pointer is saved.
Debug mode:
• Stops the analog clock
• Holds the periodic/interval timer in reset
• Prevents external trigger events from being captured
• Keeps all QADC registers and RAM accessible
Although the QADC saves a pointer to the next CCW in the current queue, software can
force the QADC to execute a different CCW by reconfiguring the QADC. When the QADC
exits debug mode, it looks at the queue operating modes, the current queue pointer, and any
pending trigger events to decide which CCW to execute.
27.3.2 Stop Mode
The QADC enters a low-power idle state whenever the QSTOP bit is set or the CPU enters
low-power stop mode.
QADC stop:
• Disables the analog-to-digital converter, effectively turning off the analog circuit
MOTOROLA
Chapter 27. Queued Analog-to-Digital Converter (QADC)
Modes of Operation
27-3
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