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Table 2-3. ColdFire CPU Registers (continued)
Name
D0-D7
A0-A7
OTHER_A7
VBR
MACSR
MASK
ACC0-ACC3
ACCext01
ACCext23
SR
PC
FLASHBAR
RAMBAR
2.4
Additions to the Instruction Set Architecture
The original ColdFire instruction set architecture (ISA) was derived from the
M68000-family opcodes based on extensive analysis of embedded application code. After
the initial ColdFire compilers were created, developers identified ISA additions that would
enhance both code density and overall performance. Additionally, as users implemented
ColdFire-based designs into a wide range of embedded systems, they identified frequently
used instruction sequences that could be improved by the creation of new instructions. This
observation was especially prevalent in development environments that made use of
substantial amounts of assembly language code.
Table 2-4 summarizes the new instructions added to Revision A+ ISA. For more details see
Section 2.14, "ColdFire Instruction Set Architecture Enhancements."
MOTOROLA
Written with
CPU Space (Rc)
MOVEC
0x(0,1)80-0x(0,1)87 No
0x(0,1)88-0x(0,1)8F No
Processor Miscellaneous Registers
0x800
No
0x801
Yes
0x804
No
0x805
No
0x806, 0x809,
No
0x80A, 0x80B
0x807
No
0x808
No
0x80E
No
0x80F
Yes
Local Memory Registers
0xC04
Yes
0xC05
Yes
Chapter 2. ColdFire Core
Additions to the Instruction Set Architecture
Register Name
Data registers 0-7 (0 = load, 1 = store)
Address registers 0-7 (0 = load, 1 = store)
A7 is user stack pointer
Other stack pointer
Vector base register
MAC status register
MAC address mask register
MAC accumulators 0-3
MAC accumulator 0, 1 extension bytes
MAC accumulator 2, 3 extension bytes
Status register
Program counter
Flash base address register
SRAM base address register
2-9
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