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26.3.2.9 Port SD Pin Assignment Register (PSDPAR)
The PSDPAR controls the pin function of port SD.
7
Field
PSDPA
1
Reset See Note 1
R/W:
R/W
Address
Figure 26-22. Port SD Pin Assignment Register (PSDPAR)
1
Reset state determined during reset configuration. PJPAn = 1 in master mode and 0 in all other modes.
Bits
7
6–0
26.3.2.10 Port AS Pin Assignment Register (PASPAR)
The PASPAR controls the pin function of port AS.
15
Field
Reset
R/W:
7
Field
PASPA3
Reset
R/W:
Address
Figure 26-23. Port AS Pin Assignment Register (PASPAR)
MOTOROLA
6
IPSBAR + 0x10_0055
Table 26-13. PSDPAR Field Descriptions
Name
PSDPA
Port SD pin assignment. This bit configures the port SD[5:0] pins for
their primary functions (SRAS, SCAS, DRAMW, SDRAM_CS[1:0],
SCKE) or digital I/O.
1 Port SD[5:0] pins configured for primary functions (SRAS, SCAS,
DRAMW, SDRAM_CS[1:0], SCKE)
0 Port SD[5:0] pin configured for digital I/O
—
Reserved, should be cleared.
12
—
R
6
5
4
PASPA2
IPSBAR + 0x10_0056
Chapter 26. General Purpose I/O Module
Memory Map/Register Definition
—
000_0000
R
Description
11
10
PASPA5
0000_0000
3
2
PASPA1
0000_0000
R/W
0
9
8
PASPA4
R/W
1
0
PASPA0
26-19
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