Supervisor Instruction Set; Pst/Ddata Specification For Supervisor-Mode Instructions - Motorola ColdFire MCF5281 User Manual

Processor Status, DDATA Definition
Table 29-23. PST/DDATA Specification for MAC Instructions (continued)
Instruction Operand Syntax
move.l Accy,Rx
move.l MACSR,CCR
move.l MACSR,Rx
move.l MASK,Rx
move.l Accext01,Rx
move.l Accext23,Rx
msac.l Ry,Rx,Accx
msac.l Ry,Rx,<ea>,Rw,Accx
msac.w Ry,Rx,Accx
msac.w Ry,Rx,<ea>,Rw,Accx

29.7.2 Supervisor Instruction Set

The supervisor instruction set has complete access to the user mode instructions plus the
opcodes shown below. The PST/DDATA specification for these opcodes is shown in
Table 29-24.
Table 29-24. PST/DDATA Specification for Supervisor-Mode Instructions
Instruction Operand Syntax
cpushl
halt
move.w SR,Dx
move.w {Dy,#imm},SR
movec Ry,Rc
rte
stldsr.w #imm
stop #imm
wdebug <ea>y
The move-to-SR, STLDSR, and RTE instructions include an optional PST = 0x3 value,
indicating an entry into user mode. Additionally, if the execution of a RTE instruction
returns the processor to emulator mode, a multiple-cycle status of 0xD is signaled.
Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted
state (PST = 0xF) display this status throughout the entire time the ColdFire processor is in
the given mode.
29-44
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1
PST = 0x1,
PST = 0xF
PST = 0x1
PST = 0x1, {PST = 0x3}
PST = 0x1
PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 3}, { PST =0xB,
DD =source operand},
PST = 0x5, {[PST = 0x9AB], DD = target address}
PST = 0x1, {PST = 0xA, DD = destination operand, PST = 0x3}
PST = 0x1,
PST = 0xE
PST = 0x1, {PST = 0xB, DD = source, PST = 0xB, DD = source}
MCF5282 User's Manual
PST/DDATA
PST/DDATA
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