Motorola ColdFire MCF5281 User Manual page 799

Address
IPSBAR +
0x1C_0010
IPSBAR +
0x1C_0014
IPSBAR +
0x1C_0018
IPSBAR +
0x1C_0020
IPSBAR +
0x1C_0022
IPSBAR +
0x1C_0024
IPSBAR +
0x1C_0026
IPSBAR +
0x1C_0027
IPSBAR +
0x1C_0080
IPSBAR +
0x1D_0000
IPSBAR +
0x1D_0002
IPSBAR +
0x1D_0008
IPSBAR +
0x1D_0010
IPSBAR +
0x1D_0014
IPSBAR +
0x1D_0018
IPSBAR +
0x1D_0020
IPSBAR +
0x1D_0024
1
The DMA module originally supported a left-justified 16-bit byte count register (BCR). This function was
later reimplemented as a right-justified 24-bit BCR. The operation of the DMA and the interpretation of
the BCR is controlled by the MPARK[BCR24BIT]. See Chapter Chapter 8, "System Control Module
(SCM)" for more details.
2
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software
reset command. That is, if channel operation is not disabled, undesirable results may occur.
MOTOROLA
Table A-3. Register Memory Map (Continued)
Name
Rx Global Mask
Rx Buffer 14 Mask
Rx Buffer 15 Mask
Error and Status
Interrupt Masks
Interrupt Flags
Rx Error Counters
Tx Error Counter
Message Buffer 0 - Message Buffer 15
Flash Registers
CFM Configuration Register
CFM Clock Divider Register
CFM Security Register
CFM Protection Register
CFM Supervisor Access Register
CFM Data Access Register
CFM User Status Register
CFM Command Register
Appendix A. Register Memory Map
Mnemonic Size
RXGMASK 32
RX14MASK 32
RX15MASK 32
ESR 16
IMASK 16
IFLAG 16
RXERRCNT 8
TXERRCNT 8
MBUFF0– 16x16bytes
MBUFF15
CFMMCR 16
CFMCLKD 8
32
CFMSEC
CFMPROT 32
CFMSACC 32
CFMDACC 32
CFMUSTAT 8
CFMCMD 8
A-21