Dma Controller Module Programming Model; Memory Map For Dma Controller Module Registers - Motorola ColdFire MCF5281 User Manual

16.4 DMA Controller Module Programming Model

This section describes each internal register and its bit assignment. Note that modifying
DMA control registers during a DMA transfer can result in undefined operation. Table 16-2
shows the mapping of DMA controller registers. Note the differences for the byte count
registers depending on the value of MPARK[BCR24BIT]. See Section 8.5.3, "Bus Master
Park Register (MPARK)" for further information.
Table 16-2. Memory Map for DMA Controller Module Registers
DMA IPSBAR
Channel Offset
0 0x100
0x104
0x108
0x10C
0x10C
0x110 DMA status register 0
(DSR0) [p. 16-10]
1 0x140
0x144
0x148
0x14C
0x14C
0x150 DMA status register 1
(DSR1) [p. 16-10]
2 0x180
0x184
0x188
0x18C
0x18C
0x190 DMA status register 2
(DSR2) [p. 16-10]
3 0x1C0
0x1C4
0x1C8
0x1CC
0x1CC
0x1D0 DMA status register 3
(DSR3) [p. 16-10]
1
The DMA module originally supported a left-justified 16-bit byte count register (BCR). This function was later reimplemented as
a right-justified 24-bit BCR. The operation of the DMA and the interpretation of the BCR is controlled by the
MPARK[BCR24BIT]. See Section 8.5.3, "Bus Master Park Register (MPARK)" for more details.
MOTOROLA
[31:24]
Source address register 0 (SAR0) [p. 16-6]
Destination address register 0 (DAR0) [p. 16-6]
DMA control register 0 (DCR0) [p. 16-8]
Byte count register 0 (BCR24BIT = 0)
Reserved
Source address register 1 (SAR1) [p. 16-6]
Destination address register 1 (DAR1) [p. 16-6]
DMA control register 1 (DCR1) [p. 16-8]
Byte count register 1 (BCR24BIT = 0)
Reserved
Source address register 2 (SAR2) [p. 16-6]
Destination address register 2 (DAR2) [p. 16-6]
DMA control register 2 (DCR2) [p. 16-8]
Byte count register 2 (BCR24BIT = 0)
Reserved
Source address register 3 (SAR3) [p. 16-6]
Destination address register 3 (DAR3) [p. 16-6]
DMA control register 3 (DCR3) [p. 16-8]
Byte count register 3 (BCR24BIT = 0)
Reserved
Chapter 16. DMA Controller Module
DMA Controller Module Programming Model
[23:16] [15:8]
1
Byte count register 0 (BCR24BIT = 1)
Reserved
1
Byte count register 1 (BCR24BIT = 1)
Reserved
1
Byte count register 2 (BCR24BIT = 1)
Reserved
1
Byte count register 3 (BCR24BIT = 1)
Reserved
[7:0]
Reserved
1
(BCR0) [p. 16-7]
Reserved
1
(BCR1) [p. 16-7]
Reserved
1
(BCR2) [p. 16-7]
Reserved
1
(BCR3) [p. 16-7]
16-5