Dmr Initialization; Dmr0 Register; Dmr0 Initialization Values - Motorola ColdFire MCF5281 User Manual

SDRAM Example
Table 15-28. DACR Initialization Values (continued)
Bits Name
3 IP
2–0 —

15.3.4 DMR Initialization

Again, in this example only the second 512-Kbyte block of each 1-Mbyte space is accessed
in each bank. In addition, the SDRAM component is mapped only to readable and writable
supervisor and user data. The DMRs have the following configuration.
31
Field
Setting
(hex)
15
Field
Setting
(hex)
With this configuration, the DMR0 = 0x0074_0075, as described in Table 15-29.
Bits Name Setting
31–18 BAM
17–16 —
15–9 —
8 WP 0
7 —
6 C/I 1
5 AM 1
4 SC 1
3 SD 0
2 UC 1
1 UD 0
0 V 1
15-22
Setting
0 Indicates precharge has not been initiated.
Reserved. Don't care.
0000_0000_0111_01xx
9
—
xxxx_xxx0_x111_0101
Figure 15-14. DMR0 Register
Table 15-29. DMR0 Initialization Values
With bits 17 and 16 as don't cares, BAM = 0x0074, which leaves bank select bits and upper 512K
select bits unmasked. Note that bits 22 and 21 are set because they are used as bank selects; bit 20 is
set because it controls the 1-Mbyte boundary address.
Reserved. Don't care.
Reserved. Don't care.
Allow reads and writes
Reserved. Don't care.
Disable CPU space access.
Disable alternate master access.
Disable supervisor code accesses.
Enable supervisor data accesses.
Disable user code accesses.
Enable user data accesses.
Enable accesses.
MCF5282 User's Manual
Description
BAM
0 074
8 7 6 5
WP — C/I AM
0075
Description
18 17
—
4 3 2 1
SC SD UC UD
MOTOROLA
16
0
V