Eport Port Interrupt Enable Register (Epier); Eport Port Data Register (Epdr); Epdd Field Descriptions; Epier Field Descriptions - Motorola ColdFire MCF5281 User Manual

Bit(s) Name
7–1 EPDDx
0 —
11.4.2.3 Edge Port Interrupt Enable Register (EPIER)
Field EPIE7
Reset
R/W
Address
Figure 11-4. EPORT Port Interrupt Enable Register (EPIER)
Bit(s) Name
7–1 EPIEx
0 —
11.4.2.4 Edge Port Data Register (EPDR)
Field
Reset
R/W
Address
MOTOROLA
Table 11-4. EPDD Field Descriptions
Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit
in EPDDR configures the corresponding pin as an input. Pin direction is independent of the
level/edge detection configuration. Reset clears EPDD7-EPDD1.
To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR
must be clear. Software can generate interrupt requests by programming the EPORT data
register when the EPDDR selects output.
1 Corresponding EPORT pin configured as output
0 Corresponding EPORT pin configured as input
Reserved, should be cleared.
7 6 5
EPIE6 EPIE5
Table 11-5. EPIER Field Descriptions
Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set,
EPORT generates an interrupt request when:
• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set.
• The corresponding pin level is low and the pin is configured for level-sensitive operation.
Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin.
Reset clears EPIE7-EPIE1.
1 Interrupt requests from corresponding EPORT pin enabled
0 Interrupt requests from corresponding EPORT pin disabled
Reserved, should be cleared.
7 6 5
EPD7 EPD6 EPD5
Figure 11-5. EPORT Port Data Register (EPDR)
Chapter 11. Edge Port Module (EPORT)
Description
4 3
EPIE4 EPIE3
0000_0000
R/W
IPSBAR + 0x0013_0003
Description
4 3
EPD4 EPD3
1111_1111
R/W
IPSBAR + 0x0013_0004
Memory Map and Registers
2 1 0
EPIE2 EPIE1 —
R
2 1 0
EPD2 EPD1 —
R
11-5