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Chapter 2
ColdFire Core
This section describes the organization of the Version 2 (V2) ColdFire
an overview of the program-visible registers. For detailed information on instructions, see
the ColdFire Family Programmer's Reference Manual.
2.1
Processor Pipelines
Figure 2-1 is a block diagram showing the processor pipelines of a V2 ColdFire core.
Instruction
Fetch
Pipeline
Operand
Execution
Pipeline
MOTOROLA
Instruction
Address
IAG
Generation
Instruction
IC
Fetch Cycle
FIFO
IB
Instruction Buffer
Decode & Select,
DSOC
Operand Fetch
Address
Generation,
AGEX
Execute
Figure 2-1. ColdFire Processor Core Pipelines
Chapter 2. ColdFire Core
®
processor core and
Address [31:0]
read_data[31:0]
write_data[31:0]
2-1
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