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Overview
Table 14-1. MCF5282 Signal Description (Continued)
Signal Name
SDRAM write enable
SDRAM bank selects
SDRAM clock enable
Reset in
Reset out
EXTAL
XTAL
Clock output
Clock mode
Reset configuration
External interrupts
Management data
Management data clock EMDC
Transmit clock
Transmit enable
Transmit data 0
Collision
Receive clock
14-4
Abbreviation
DRAMW
Asserted to signify that a DRAM write
cycle is underway. Negated to indicate
a read cycle.
SDRAM_CS[1:0]
Interface to the chip-select lines of the
SDRAMs within a memory block.
SCKE
SDRAM clock enable.
Clock and Reset Signals
RSTI
Asserted to enter reset exception
processing.
RSTO
Automatically asserted with RSTI.
Negation indicates that the PLL has
regained its lock.
EXTAL
Driven by an external clock except
when used as a connection to the
external crystal.
XTAL
Internal oscillator connection to the
external crystal.
CLKOUT
Reflects the system clock.
Chip Configuration Module
CLKMOD[1:0]
Clock mode select
RCON
Reset configuration select
External Interrupt Signals
IRQ[7:1]
External interrupt sources.
Ethernet Module Signals
EMDIO
Transfers control information between
the external PHY and the media
access controller.
Provides a timing reference to the
PHY for data transfers on the EMDIO
signal.
ETXCLK
Provides a timing reference for
ETXEN, ETXD[3:0], and ETXER.
ETXEN
Indicates when valid nibbles are
present on the MII.
ETXD0
Serial output Ethernet data.
ECOL
Asserted to indicate a collision.
ERXCLK
Provides a timing reference for
ERXDV, ERXD[3:0], and ERXER.
MCF5282 User's Manual
Function
I/O
Page
O
14-21
O
14-21
O
14-21
I
14-22
O
14-22
I
14-22
O
14-22
O
14-22
I
14-22
I
14-22
I
14-23
I/O
14-23
O
14-23
I
14-23
O
14-23
O
14-23
I
14-24
I
14-24
MOTOROLA
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