Register Descriptions; Interrupt Pending Registers (Iprhn, Iprln) - Motorola ColdFire MCF5281 User Manual

Register Descriptions

Table 10-3. Interrupt Controller Memory Map (continued)
Module Offset
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
0x7C
0x80-0xDC
0xE0
0xE4
0xE8
0xEC
0xF0
0xF4
0xF8
0xFC
10.3 Register Descriptions

10.3.1 Interrupt Pending Registers (IPRHn, IPRLn)

The IPRHn and IPRLn registers, Figure 10-1 and Figure 10-2, are each 32 bits in size, and
provide a bit map for each interrupt request to indicate if there is an active request (1 =
active request, 0 = no request) for the given source. The state of the interrupt mask register
does not affect the IPRn. The IPRn is cleared by reset. The IPRn is a read-only register, so
any attempted write to this register is ignored. Bit 0 is not implemented and reads as a zero.
10-6
Bits[31:24] Bits[23:16]
ICR32 ICR33
ICR36 ICR37
ICR40 ICR41
ICR44 ICR45
ICR48 ICR49
ICR52 ICR53
ICR56 ICR57
ICR60 ICR61
SWIACK
L1IACK
L2IACK
L3IACK
L4IACK
L5IACK
L6IACK
L7IACK
MCF5282 User's Manual
Bits[15:8]
ICR34
ICR38
ICR42
ICR46
ICR50
ICR54
ICR58
ICR62
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bits[7:0]
ICR35
ICR39
ICR43
ICR47
ICR51
ICR55
ICR59
ICR63
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