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The mov.l instruction that stores the accumulator to an integer register (Rz) stalls until the
program-visible copy of the accumulator is available. Figure 3-8 shows EMAC timing.
DSOC
AGEX
EMAC EX1
EMAC EX2
EMAC EX3
EMAC EX4
Accumulator 0
In Figure 3-8, the OEP stalls the store-accumulator instruction for 3 cycles: the depth of the
EMAC pipeline minus 1. The minus 1 factor is needed because the OEP and EMAC
pipelines overlap by a cycle, the AGEX stage. As the store-accumulator instruction reaches
the AGEX stage where the operation is performed, the just-updated accumulator 0 value is
available.
As with change or use stalls between accumulators and general-purpose registers,
introducing intervening instructions that do not reference the busy register can reduce or
eliminate sequence-related store-MAC instruction stalls. In fact, a major benefit of the
EMAC is the addition of three accumulators to minimize stalls caused by exchanges
between the accumulator(s) and the general-purpose registers.
3.5.2
Data Representation
MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a
unique operand type.
• Two's complement signed integer: In this format, an N-bit operand value lies in the
(N-1)
range -2
• Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand
N
< 2
- 1. The binary point is right of the lsb.
• Two's complement, signed fractional: In an N-bit number, the first bit is the sign bit.
The remaining bits signify the first N-1 bits after the binary point. Given an N-bit
number, a
a
N-1
MOTOROLA
mac
mac
mac
Figure 3-8. EMAC-Specific OEP Sequence Stall
(N-1)
< operand < 2
- 1. The binary point is right of the lsb.
a
... a
a
a
, its value is given by the equation in Figure 3-9.
N-2
N-3
2
1
0
Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC)
Three-cycle
regBusy stall
mov
mov
mac
mac
mac
old
EMAC Instruction Set Summary
mov
mov
new
3-13
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