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Chapter 22
Queued Serial Peripheral Interface
(QSPI) Module
This chapter describes the queued serial peripheral interface (QSPI) module. Following a
feature set overview is a description of operation including details of the QSPI's internal
RAM organization. The chapter concludes with the programming model and a timing
diagram.
22.1 Overview
The queued serial peripheral interface module provides a serial peripheral interface with
queued transfer capability. It allows users to queue up to 16 transfers at once, eliminating
CPU intervention between transfers. Transfer RAM in the QSPI is indirectly accessible
using address and data registers.
22.2 Features
• Programmable queue to support up to 16 transfers without user intervention
• Supports transfer sizes of 8 to 16 bits in 1-bit increments
• Four peripheral chip-select lines for control of up to 15 devices
• Baud rates from 129.4 Kbps to 16.67 Mbps at 66 MHz
• Programmable delays before and after transfers
• Programmable QSPI clock phase and polarity
• Supports wraparound mode for continuous transfers
22.3 Module Description
The QSPI module communicates with the integrated ColdFire CPU using internal memory
mapped registers starting at IPSBAR + 0x340. See Section 22.5, "Programming Model." A
block diagram of the QSPI module is shown in Figure 22-1.
MOTOROLA
Chapter 22. Queued Serial Peripheral Interface (QSPI) Module
22-1
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