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Digital Control Subsystem
27.7.3.5 Comparator
The comparator output feeds into the SAR, which accumulates the A/D conversion result
sequentially, beginning with the MSB.
27.7.3.6 Bias
The bias circuit is controlled by the STOP signal to power-up and power-down all the
analog circuits.
27.7.3.7 Successive Approximation Register (SAR)
The input of the SAR is connected to the comparator output. The SAR sequentially receives
the conversion value one bit at a time, starting with the MSB. After accumulating the 10
bits of the conversion result, the SAR data is transferred to the appropriate result location,
where it may be read by user software.
27.7.3.8 State Machine
The state machine generates all timing to perform an A/D conversion. An internal
start-conversion signal indicates to the A/D converter that the desired channel has been sent
to the MUX. CCW[IST[1:0]] denotes the desired sample time. CCW[BYP] determines
whether to bypass the sample amplifier. Once the end of conversion has been reached a
signal is sent to the queue control logic indicating that a result is available for storage in the
result RAM.
27.8 Digital Control Subsystem
The digital control subsystem includes the control logic to sequence the conversion activity,
the system clock and periodic/interval timer, control and status registers, the conversion
command word table RAM, and the result word table RAM.
The central element for control of QADC conversions is the 64-entry conversion command
word (CCW) table. Each CCW specifies the conversion of one input channel. Depending
on the application, one or two queues can be established in the CCW table. A queue is a
scan sequence of one or more input channels. By using a pause mechanism, subqueues can
be created in the two queues. Each queue can be operated using one of several different scan
modes. The scan modes for queue 1 and queue 2 are programmed in control registers
QACR1 and QACR2. Once a queue has been started by a trigger event (any of the ways to
cause the QADC to begin executing the CCWs in a queue or subqueue), the QADC
performs a sequence of conversions and places the results in the result word table.
MOTOROLA
Chapter 27. Queued Analog-to-Digital Converter (QADC)
27-37
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