Qadc Control Register 0 (Qacr0); Qacr0 Field Descriptions - Motorola ColdFire MCF5281 User Manual

Register Descriptions
15
Field MUX
Reset
R/W: R/W
7
Field —
Reset
R/W: R
Address
Bit(s) Name
15 MUX
14–13 —
12 TRG
11–7 —
6–0 QPR
27-12
14 13
—
R
6 5
QPR6 QPR5
IPSBAR + 0x19_000a, 0x19_000b
Figure 27-8. QADC Control Register 0 (QACR0)
Table 27-4. QACR0 Field Descriptions
Externally multiplexed mode. Configures the QADC for operation in externally multiplexed
mode, which affects the interpretation of the channel numbers and forces the MA[1:0] signals
to be outputs.
1 Externally multiplexed, up to 18 possible channels
0 Internally multiplexed, up to 8 possible channels
Reserved, should be cleared.
Trigger assignment. Determines the queue assignment of the ETRIG[2:1] signals.
1 ETRIG1 triggers queue 2; ETRIG2 triggers queue 1.
0 ETRIG1 triggers queue 1; ETRIG2 triggers queue 2.
Reserved, should be cleared.
Prescaler clock divider. Selects the system clock divisor to generate the QADC clock as
Table 27-5 shows. The resulting QADC clock rate can be given as:
where:
1 ≤ QPR[6:0] ≤ 127.
If QPR[6:0] = 0, then the QPR register field value is read as a 1 and the prescaler divisor is 2.
The prescaler should be selected so that the QADC clock rate is within the required f
range. See MCF5282 Electrical Characteristics.
MCF5282 User's Manual
12 11
TRG
0000_0000
R/W
4 3
QPR4 QPR3 QPR2
0001_0011
R/W
Description
f
f =
QCLK
2(QPR[6:0] + 1)
—
R
2 1
QPR1 QPR0
SYS
MOTOROLA
8
0
QCLK