Gpt Channel Registers (Gptcn); Pulse Accumulator Control Register (Gptpactl); Gpt Channel[0:3] Register (Gptcn); Gptcn Field Descriptions - Motorola ColdFire MCF5281 User Manual

20.5.14 GPT Channel Registers (GPTCn)

15
Field
Reset
R/W
Address
Figure 20-16. GPT Channel[0:3] Register (GPTCn)
Bit(s) Name
15–0 CCNT

20.5.15 Pulse Accumulator Control Register (GPTPACTL)

Field
Reset
R/W
Address
Figure 20-17. Pulse Accumulator Control Register (GPTPACTL)
Bit(s) Name
7 —
6 PAE
5 PAMOD
MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB)
0000_0000_0000_0000
IPSBAR + 0x1A_0010, 0x1A_0012, 0x1A_0014, 0x1A_0016,
0x1B_0010, 0x1B_0012, 0x1B_0014, 0x1B_0016
Table 20-17. GPTCn Field Descriptions
When a channel is configured for input capture (IOSn = 0), the GPT channel registers
latch the value of the free-running counter when a defined transition occurs on the
corresponding input capture pin.
When a channel is configured for output compare (IOSn = 1), the GPT channel
registers contain the output compare value.
To ensure coherent reading of the GPT counter, such that a timer rollover does not
occur between back-to-back 8-bit reads, it is recommended that only word (16-bit)
accesses be used. These bits are read anytime, write anytime (for the output compare
channel); writing to the input capture channel has no effect.
7 6 5
— PAE PAMOD PEDGE
IPSBAR + 0x1A_0018, 0x1B_0018
Table 20-18. GPTPACTL Field Descriptions
Reserved, should be cleared.
Enables the pulse accumulator.
1 Pulse accumulator enabled
0 Pulse accumulator disabled
Note: The pulse accumulator can operate in event mode even when the GPT enable
bit, GPTEN, is clear.
Pulse accumulator mode. Selects event counter mode or gated time accumulation
mode.
1 Gated time accumulation mode
0 Event counter mode
CCNT
R/W
Description
4 3
CLK PAOVI
0000_0000
R/W
Description
Memory Map and Registers
0
0
PAI
20-13