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8
Assuming a reference is available at power up, lock time is measured from the time V
to RSTO negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up
time must be added to the PLL lock time to determine the total start-up time.
9
PLL is operating in 1:1 PLL mode.
10
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
f
. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
sys
signal. Noise injected into the PLL circuitry via V
increase the Cjitter percentage for a given interval
11
Based on slow system clock of 40 MHz measured at f
33.5 QADC Electrical Characteristics
Parameter
Analog Supply, with reference to V
1
Internal Digital Supply
, with reference to V
Reference Supply, with reference to V
V
Differential Voltage
SS
2
V
Differential Voltage
DD
V
Differential Voltage
REF
V
to V
Differential Voltage
RH
DDA
V
to V
Differential Voltage
RL
SSA
V
to V
Differential Voltage
DDH
DDA
4, 5, 6
Maximum Input Current
1
For internal digital supply of V
2
Refers to allowed random sequencing of power supplies.
3
Refers to allowed random sequencing of power supplies.
4
Transitions within the limit do not affect device reliability or cause permanent damage. Exceeding limit may cause
permanent conversion error on stressed channels and on unstressed channels.
5
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values using V
calculated values.
6
Condition applies to one pin at a time.
Table 33-6. QADC Electrical Specifications (Operating)
±
(V
and V
= 5.0 V
0.5V, V
DDH
DDA
dc
Parameter
Analog Supply
V
Differential Voltage
SS
2
Reference Voltage Low
2
Reference Voltage High
V
Differential Voltage
REF
MOTOROLA
DDPLL
Table 33-5. QADC Absolute Maximum Ratings
SSA
SS
RL
3
= 3.3V typical.
DD
= V
POSCLAMP
DDA
= 2.7-3.6V, V
and V
DD
SS
Chapter 33. Electrical Characteristics
and V
and variation in crystal oscillator frequency
SSPLL
max.
sys
Symbol
Min
V
–0.3
DDA
V
–0.3
DD
V
–0.3
RH
V
– V
–0.1
SS
SSA
V
– V
–6.0
DD
DDA
V
– V
–0.3
RH
RL
V
– V
–6.0
RH
DDA
V
– V
–0.3
RL
SSA
V
– V
–1.0
DDH
DDA
I
–25
MA
+ 0.3V and V
= –0.3 V, then use the larger of the
NEGCLAMP
= 0 V
, FQCLK = 2.0 MHz, TA within operating temperature range)
SSA
dc
Symbol
Min
V
3.3
DDA
V
– V
-100
SS
SSA
V
V
RL
SSA
V
V
RH
DDA
V
– V
3.3
RH
RL
QADC Electrical Characteristics
and V
are valid
DD
DDPLL
Max
6.0
4.0
6.0
0.1
4.0
6.0
6.0
0.3
1.0
25
1
Max
5.5
100
V
+ 0.1
SSA
– 0.1
V
DDA
5.5
Unit
V
V
V
V
V
V
V
V
V
mA
Unit
V
mV
V
V
V
33-7
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