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FCE
?
False
False
Hash Search
Group Table
Match
?
False
Reject Frame
Flush from FIFO
NOTES:
FCE - field in RCR register (Flow Control Enable)
I/G - Individual/Group bit in Destination Address (least significant bit in first byte received in MAC frame)
Figure 17-3. Ethernet Address Recognitionq—Microcode Decisions
17.4.9 Hash Algorithm
The hash table algorithm used in the group and individual hash filtering operates as follows.
The 48-bit destination address is mapped into one of 64 bits, which are represented by 64
bits stored in GAUR, GALR (group address hash match) or IAUR, IALR (individual
address hash match). This mapping is performed by passing the 48-bit address through the
on-chip 32-bit CRC generator and selecting the 6 most significant bits of the CRC-encoded
result to generate a number between 0 and 63. The MSB of the CRC result selects GAUR
(MSB = 1) or GALR (MSB = 0). The least significant 5 bits of the hash result select the bit
within the selected register. If the CRC generator selects a bit that is set in the hash table,
the frame is accepted; otherwise, it is rejected.
For example, if eight group addresses are stored in the hash table and random group
addresses are received, the hash table prevents roughly 56/64 (or 87.5%) of the group
address frames from reaching memory. Those that do reach memory must be further filtered
by the processor to determine if they truly contain one of the eight desired addresses.
MOTOROLA
Receive Address
Recognition
Group
I/G Address
True
True
Pause Address
?
Receive Frame
True
Receive Frame
Chapter 17. Fast Ethernet Controller (FEC)
Individual
?
False
Hash Search
Individual Table
True
Match
?
False
Receive Frame
Reject Frame
Flush from FIFO
Functional Description
True
Exact Match
?
Receive Frame
17-13
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