Transfer Size Encoding - Motorola ColdFire MCF5281 User Manual

MCF5282 External Signals
Note that for misaligned transfers, SIZ[1:0] indicate the size of each transfer. For example,
if a longword access occurs at a misaligned offset of 0x1, a byte is transferred first (SIZ[1:0]
= 01), a word is next transferred at offset 0x2 (SIZ[1:0] = 10), then the final byte is
transferred at offset 0x4 (SIZ[1:0] = 01).
For aligned transfers larger than the port size, SIZ[1:0] behaves as follows:
• If bursting is used, SIZ[1:0] stays at the size of transfer.
• If bursting is inhibited, SIZ[1:0] first shows the size of the transfer and then shows
the port size.
For burst-inhibited transfers, SIZ[1:0] changes with each TS assertion to reflect the next
transfer size. For transfers to port sizes smaller than the transfer size, SIZ[1:0] indicates the
size of the entire transfer on the first access and the size of the current port transfer on
subsequent transfers. For example, for a longword write to an 8-bit port, SIZ[1:0] = 00 for
the first byte transfer and 01 for the next three.
These pins can also be configured as GPIO PE[3:2] or SYNCA, SYNCB.
14.2.1.9 Transfer Start (TS)
The MCF5282 asserts TS during the first CLKOUT cycle of a transfer when address and
attributes (TIP, R/W, and SIZ[1:0]) are valid. TS is negated in the following CLKOUT
cycle.
This pin can also be configured as GPIO PE1 or SYNCA.
14.2.1.10 Transfer In Progress (TIP)
The TIP output is asserted indicating a bus transfer is in progress. It is negated during idle
bus cycles. Note that TIP is held asserted on back-to-back cycles.
TIP is not asserted during SDRAM accesses.
This pin can also be configured as GPIO PE0 or SYNCB.
14.2.1.11 Chip Selects (CS[6:0])
Each chip select can be programmed for a base address location and for masking addresses,
14-20
Table 14-6. Transfer Size Encoding
SIZ[1:0]
00
01
10
11
NOTE:
MCF5282 User's Manual
Transfer Size
Longword
Byte
Word
16-byte line
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