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Overview
15.1.2 Block Diagram and Major Components
The basic components of the SDRAM controller are shown in Figure 15-1.
DRAM Controller Module
D[31:0] internal
Q[31:0] internal
A[31:0]
Internal
Bus
Memory Block 0 Hit Logic
DRAM Address/Control Register 0
Memory Block 1 Hit Logic
DRAM Address/Control Register 1
Figure 15-1. Synchronous DRAM Controller Block Diagram
The DRAM controller's major components are as follows:
• DRAM address and control registers (DACR0 and DACR1)—The DRAM
controller consists of two configuration register units, one for each supported
memory block. DACR0 is accessed at IPSBAR + 0x048; DACR1 is accessed at
IPSBAR + 0x050. The register information is passed on to the hit logic.
• Control logic and state machine—Generates all SDRAM signals, taking hit
information and bus-cycle characteristic data from the block logic in order to
generate SDRAM accesses. Handles refresh requests from the refresh counter.
— DRAM control register (DCR)—Contains data to control refresh operation of the
DRAM controller. Both memory blocks are refreshed concurrently as controlled
by DCR[RC].
— Refresh counter—Determines when refresh should occur; controlled by the
value of DCR[RC]. It generates a refresh request to the control block.
• Hit logic—Compares address and attribute signals of a current SDRAM bus cycle
to both DACRs to determine if an SDRAM block is being accessed. Hits are passed
to the control logic along with characteristics of the bus cycle to be generated.
15-2
(DACR0)
(DACR1)
MCF5282 User's Manual
Data
Generation
Address
Multiplexing
Control Logic
and
State Machine
DRAM Control
Register (DCR)
Refresh Counter
D[31:0]
D[31:0]
A[31:0]
SCAS
SRAS
SCKE
SDRAM_CS[1:0]
DRAMW
BS[3:0]
MOTOROLA
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