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Table 4-7. External Fetch Size Based on Miss Address and CLNF
4.4.2.2
Access Control Registers (ACR0, ACR1)
The ACRs provide a definition of memory reference attributes for two memory regions
(one per ACR). This set of effective attributes is defined for every memory reference using
the ACRs or the set of default attributes contained in the CACR. The ACRs are examined
for every processor memory reference that is not mapped to the Flash or SRAM memories.
The ACRs are 32-bit write-only supervisor control register. They are accessed in the CPU
address space via the MOVEC instruction with an Rc encoding of 0x004 and 0x005. The
ACRs can be read when in background debug mode (BDM). At system reset, both registers
are cleared.
31
Field
Reset
R/W
15
14
Field EN
SM
Reset
R/W
Figure 4-3. Access Control Registers (ACR0, ACR1)
Bits
Name
31–24
AB
Address base. This 8-bit field is compared to address bits [31:24] from the processor's local bus under
control of the ACR address mask. If the address matches, the attributes for the memory reference are
sourced from the given ACR.
22–16
AM
Address mask. This 8-bit field can mask any bit of the AB field comparison. If a bit in the AM field is
set, then the corresponding bit of the address field comparison is ignored.
15
EN
Enable. The EN bit defines the ACR enable. Hardware reset clears this bit, disabling the ACR.
0 ACR disabled
1 ACR enabled
MOTOROLA
CLNF[1:0]
00
00
Line
01
Line
10
Line
11
Line
AB
13
12
—
Table 4-8. ACR Field Descriptions
Chapter 4. Cache
Longword Address Bits
01
10
Line
Line
Line
Longword
Line
Line
Line
Line
24
23
0000_0000_0000_0000
W
7
6
CM
0000_0000_0000_0000
W
Description
Cache Programming Model
11
Longword
Longword
Line
Line
AM
5
4
3
2
1
BUFW
—
WP
16
0
—
4-11
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