Pit Control And Status Register (Pcsr); Pcsr Field Descriptions - Motorola ColdFire MCF5281 User Manual

Memory Map and Registers

19.5.2.1 PIT Control and Status Register (PCSR)

15
Field
Reset
R/W
7
Field —
Reset
R/W R
Address IPSBAR + 0x0015_0000 and 0x0015_0001 (PIT0); 0x0016_0000 and 0x0016_0001 (PIT1); 0x0017_0000
Figure 19-2. PIT Control and Status Register (PCSR)
Bit(s) Name
15–12 —
11–8 PRE
7 —
19-4
—
R
6 5
DOZE HALTED OVW
and 0x0017_0001 (PIT2); 0x0018_0000 and 0x0018_0001 (PIT3)
Table 19-3. PCSR Field Descriptions
Reserved, should be cleared.
Prescaler. The read/write prescaler bits select the system clock divisor to generate the PIT
clock. To accurately predict the timing of the next count, change the PRE[3:0] bits only when
the enable bit (EN) is clear. Changing the PRE[3:0] resets the prescaler counter. System reset
and the loading of a new value into the counter also reset the prescaler counter. Setting the EN
bit and writing to PRE[3:0] can be done in this same write cycle. Clearing the EN bit stops the
prescaler counter.
PRE System Clock Divisor
0000
0001
0010
0011
0100
0101
0110
0111
Reserved.
MCF5282 User's Manual
12 11
PRE3 PRE2
0000_0000
4 3
PIE PIF
0000_0000
R/W
Description
PRE
2 1000
4 1001
8 1010
16 1011
32 1100
64 1101
128 1110
256 1111
10 9 8
PRE1 PRE0
R/W
2 1 0
RLD EN
System Clock Divisor
512
1,024
2,048
4,096
8,192
16,384
32,768
65,536
MOTOROLA