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Memory Map and Registers
Bit(s)
Name
7–0
OMx/OLx
20.5.9 GPT Control Register 2 (GPTCTL2)
Field
EDG3B
Reset
R/W
Address
Figure 20-11. GPT Control Register 2 (GPTCTL2)
Bit(s)
Name
7–0
EDGn[B:A]
20.5.10 GPT Interrupt Enable Register (GPTIE)
Field
Reset
R/W
Address
Figure 20-12. GPT Interrupt Enable Register (GPTIE)
20-10
Table 20-11. GPTCL1 Field Descriptions
Output mode/output level. Selects the output action to be taken as a result of a
successful output compare on each channel. When either OMn or OLn is set and the
IOSn bit is set, the pin is an output regardless of the state of the corresponding DDR
bit. These bits are read anytime, write anytime.
00 GPT disconnected from output pin logic
01 Toggle OCn output line
10 Clear OCn output line
11 Set OCn line
Note: Channel 3 shares a pin with the pulse accumulator input pin. To use the PAI
input, clear both the OM3 and OL3 bits and clear the OC3M3 bit in the output compare
3 mask register.
7
6
5
EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B
IPSBAR + 0x1A_000B, 0x1B_000B
Table 20-12. GPTLCTL2 Field Descriptions
Input capture edge control. Configures the input capture edge detector circuits for each
channel. These bits are read anytime, write anytime.
00 Input capture disabled
01 Input capture on rising edges only
10 Input capture on falling edges only
11 Input capture on any edge (rising or falling)
7
6
5
—
IPSBAR + 0x1A_000C, 0x1B_000C
MCF5282 User's Manual
Description
4
3
2
0000_0000
R/W
Description
4
3
CI
0000_0000
R/W
1
0
EDG0A
0
MOTOROLA
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