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CFM Operation
6.4.3.1
Setting the CFMCLKD Register
Prior to issuing any program or erase commands, CFMCLKD must be written to set the
Flash state machine clock (FCLK). The CFM module runs at the system clock
frequency ÷ 2, but FCLK must be divided down from this frequency to a frequency
between 150 kHz and 200 kHz. Use the following procedure to set the PRDIV8 and
DIV[5:0] bits in CFMCLKD:
÷ 2 is greater than 12.8 MHz, PRDIV8 = 1; otherwise PRDIV8 = 0.
1. If f
SYS
2. Determine DIV[5:0] by using the following equation. Keep only the integer portion
of the result and discard any fraction. Do not round the result.
3. Thus the Flash state machine clock will be:
Consider the following example for f
So, for f
= 66 MHz, writing 0x54 to CFMCLKD will set f
SYS
a valid frequency for the timing of program and erase operations.
6-18
DIV[5:0] =
2 x 200kHz x (1 + (PRDIV8 x 7))
f
=
CLK
2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7))
= 66 MHz:
SYS
DIV[5:0] =
2 x 200kHz x (1 + (PRDIV8 x 7))
=
400 kHz x (1 + (1 x 7))
f
=
CLK
2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7))
66 MHz
=
2 x (20 + 1) x (1 + (1 x 7))
MCF5282 User's Manual
f
SYS
f
SYS
f
SYS
66 MHz
= 20
f
SYS
= 196.43 kHz
CLK
to 196.43 kHz which is
MOTOROLA
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