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Signal Name
Address and Transfer Attributes
ADDR[31:0]
Address Bus
R/W
Read/Write
TSIZ[1:0]
Transfer Size
TC[2:0]
Transfer Code
Transfer Request/Transfer Busy
TREQ
Transfer Request
TBUSY
Transfer Busy
Data
DATA[31:0]
Data Bus
Transfer Cycle Termination and Status
TA
Transfer Acknowledge
TEA
Transfer Error
Acknowledge
ABORT
Abort
Power Management
LPMD[1:0]
Low-Power Modes
Debug
DBGACK
Debug Mode
2.8.4 Bus Operation
The following sections provide a functional description of the system bus, the signals
that control it, and the bus cycles provided for data transfer operations. They also
describe the error conditions and reset operation.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 2-2 M•CORE Bus Signals
Pins
Active
I/O
32
High
O
1
High
O
2
High
O
3
High
O
1
Low
O
1
Low
O
O
32
High
I
1
Low
I
1
Low
I
1
Low
O
2
Low
O
1
Low
O
INTEGER CPU
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Description
Driven by the M•CORE to specify the physical address of
the bus transaction.
Driven by the M•CORE along with the address. Driven
high indicates that a read access is in progress. Driven
low indicates that a write access is in progress.
Driven by the M•CORE along with the address. Specifies
the data transfer size for the transaction.
Driven by the M•CORE along with the address. Indicates
the type of access for the current bus cycle.
Driven by the M•CORE along with the address and trans-
fer attributes to indicate that a new access has been
requested.
Driven by the M•CORE to indicate that an access is in
progress. This signal is driven for the duration of a cycle
and may be held asserted for multiple transfers.
Driven by the M•CORE when it "owns" the bus and it initi-
ated a write transaction to a slave device. Eight (byte), 16
(halfword), or 32 (word) bits of data can be transferred
per access.
Driven by the slave in a read transaction. Eight (byte), 16
(halfword), or 32 (word) bits of data can be transferred
per access.
Driven by the slave device to which the current transac-
tion was addressed. Indicates that the slave has received
the data on the write cycle or returned data on the read
cycle.
Driven by the slave device to which the current transac-
tion was addressed. Indicates that an error condition has
occurred during the bus cycle.
Driven by the M•CORE to indicate that the transfer is to
be aborted immediately.
Driven by the M•CORE to indicate whether the core is
running in normal mode or has just executed a low power
mode instruction.
Driven by the M•CORE to indicate that debug mode has
been entered.
MOTOROLA
2-11
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