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16.3.5 Test Reset (TRST)
The test reset input is used to reset the OnCE controller externally by placing the
OnCE control logic in a test logic reset state. OnCE operation is disabled in the reset
controller and reserved states.
16.3.6 Debug Event (DE)
The debug event (DE) pin is a bidirectional open drain pin. As an input, DE provides a
fast means of entering debug mode from an external command controller. As an out-
put, this pin provides a fast means of acknowledging debug mode entry to an external
command controller.
The assertion of this pin by a command controller causes the CPU to finish the cur-
rent instruction being executed, save the instruction pipeline information, enter debug
mode, and wait for commands to be entered from the TDI line. If DE was used to
enter debug mode, then DE must be negated after the OnCE responds with an
acknowledgment and before sending the first OnCE command.
The assertion of this pin by the CPU acknowledges that it has entered debug mode
and is waiting for commands to be entered from the TDI line.
16.4 OnCE Controller and Serial Interface
Figure 16-3 is a block diagram of the OnCE controller and serial interface.
ISBKPT
ISTRACE
ISDR
Figure 16-3 OnCE Controller and Serial Interface
MOTOROLA
16-4
Freescale Semiconductor, Inc.
OnCE Command Register
OnCE Decoder
.
.
Register Write
Register Read
CPU Control/Status
OnCE™ DEBUG MODULE
For More Information On This Product,
Go to: www.freescale.com
.
TAP
Controller
Status and Control
Registers
Mode Select
REFERENCE MANUAL
.
TDI
TCK
.
TMS
TDO
MMC2001
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