Table of Contents
Advertisement
The FIFO is not affected by operations performed in debug mode, except for incre-
menting the FIFO pointer when the FIFO is read. When debug mode is entered, the
FIFO counter points to the FIFO register containing the address of the oldest of the
eight change-of-flow prefetches. The first FIFO read obtains the oldest address, and
the following FIFO reads return the other addresses from the oldest to the newest (in
order of execution).
To ensure FIFO coherence, a complete set of eight reads of the FIFO must be per-
formed. Each read increments the FIFO pointer, causing it to point to the next loca-
tion. After eight reads, the pointer points to the same location as before the start of
the read procedure.
16.12.1 Reserved Test Control Registers (Reserved, MEM_BIST, FTCR, LSRL)
These registers are reserved for factory testing.
To prevent damage to the device or system, do not access these
registers during normal operation.
16.13 Serial Protocol Description
The following protocol permits an efficient means of communication between the
OnCE external command controller and the MMC2001. Before starting any debug-
ging activity, the external command controller must wait for an acknowledgment that
the device has entered debug mode. The external command controller communicates
with the device by sending 8-bit commands to the OnCE command register and 16 to
128 bits of data to one of the other OnCE registers. Both commands and data are
sent or received LSB first. After sending a command, the external command control-
ler must wait for the processor to acknowledge execution of certain commands before
it can properly access another OnCE register.
16.13.1 OnCE Commands
The OnCE commands can be classified as follows:
• Read commands (the device delivers the required data)
• Write commands (the device receives data and writes the data in one of the
OnCE registers)
• Commands that do not have data transfers associated with them.
The commands are eight bits long and have the format shown in Figure 16-4.
16.14 Target Site Debug System Requirements
A typical debug environment consists of a target system in which the MMC2001
resides in the user-defined hardware.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
WARNING
OnCE™ DEBUG MODULE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
16-21
Advertisement
Table of Contents
