Bus Signals; Signal Relationships To Clocks - Motorola M-CORE MMC2001 Series Reference Manual

of the cycle as well as the address space and size of the transfer. The selected device
then controls the length of the cycle with the signal(s) used to terminate the cycle.
Access requests are generated in an overlapped fashion in order to support sus-
tained single-cycle transfers.
Inputs to the M•CORE are sampled synchronously and must be stable during the
sample windows defined in Figure 2-4. If an input makes a transition during the win-
dow time period, the level recognized by the M•CORE is not predictable.
Outputs from the M•CORE change on one of the two clock edges, depending on the
signal class.
CLK
tsu = time set up
th = time hold

2.8.2 Bus Signals

Figure 2-5 shows the M•CORE bus signals arranged by functional group.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
tsu0
tsu1
Figure 2-4 Signal Relationships to Clocks
INTEGER CPU
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th0
th1
tsu2 th2
tsu3 th3
MOTOROLA
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