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TC — Prefetch Transfer Code
This control field is used to drive the CPU TC[2:0] outputs on the first instruction
prefetch caused by issuing a OnCE command with the GO bit set and not ignored. It
should typically be set to indicate a supervisor instruction access, i.e., 0b110. This
field should be restored to its original value after a debug session is completed, i.e.,
when a OnCE command is issued with the GO and EX bits set and not ignored.
C.10.12 Write-Back Bus Register (WBBR)
The write-back bus register (WBBR) is used as a means of passing operand informa-
tion between the CPU and the external command controller.
To update a processor resource, this register is initialized with a data value to be writ-
ten, and a mov instruction is executed which uses this value as a write-back data
value. The FFY bit in the control state register forces the value of the WBBR to be
substituted for the normal source value of a mov instruction, thus allowing updates to
processor registers to be performed.
C.10.13 Processor Status Register (PSR)
The OnCE processor status register (PSR) is a 32-bit latch used to read or write the
M•CORE processor status register. Whenever the external command controller
needs to save or modify the contents of the M•CORE processor status register, this
register is used. This register is affected by the operations performed in debug mode
and must be restored by the external command controller when returning to normal
mode.
C.10.14 Reserved Test Control Registers (Reserved, MEM_BIST, FTCR, LSRL)
These registers are reserved for factory testing.
To prevent damage to the device or system, do not access these
registers during normal operation.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
WARNING
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
C-53
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