Table of Contents
Advertisement
C.8.2 ISPI Control Register
The ISPI control register (SPCR), along with the ISPI interval control register, controls
the operation of the ISPI. Follow this sequence when changing operating modes:
1. Disable the ISPI (COUNT = 0).
2. Wait for any transfer to complete (XCH bit clear).
3. Update to the new mode.
4. Re-enable the ISPI (COUNT = newcount).
SPCR — ISPI Control Register
15
14
13
12
R
SPI_
DOZE
SNS
DRV
EN
W
RESET:
0
0
0
0
DOZE — Doze Mode
When the CPU executes a doze instruction and the system is placed in doze mode,
the DOZE bit affects operation of the ISPI. When this bit is set, the ISPI is disabled in
doze mode.
0 = ISPI unaffected in doze mode
1 = ISPI disabled in doze mode
At reset, this bit is cleared to zero.
SPI_EN — ISPI Enable
In either master mode, this bit controls the value of the SPI_EN pin. The sense of the
SPI_EN pin is determined by the SNS bit. In interval mode, the SPI_EN pin is
asserted only when XCH is active. The SPI_EN bit must be programmed to a one for
any master mode transfer to occur. In slave mode, the ISPI state machine uses the
input value on the SPI_EN pin, and this register bit is ignored. Further, the SPI_EN
register bit will not reflect the value of the SPI_EN pin in slave mode.
0 = Negated
1 = Asserted
SNS — SPI_EN Sense
The SNS bit controls the sense of the SPI_EN pin relative to the SPI_EN register bit
in the ISPI control register. This is required because in interval mode, the state
machine must assert and then negate the SPI_EN pin. The SNS bit has an affect only
when the SPI_EN pin is an output. If the SPI_EN pin is an input, then it is active low,
and the SNS bit has no effect.
0 = SPI_EN pin is active low
1 = SPI_EN pin is active high
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
11
10
9
8
IRQ_
MSTR
PHA
POL
EN
0
0
0
0
Figure C-33 ISPI Control Register
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
7
6
5
4
SPIGP
BAUD RATE
0
0
0
0
10008002
3
2
1
0
CLOCK COUNT
0
0
0
0
MOTOROLA
C-31
Advertisement
Table of Contents
