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16.1 Overview
The on-chip emulation (OnCE™) circuitry provides a simple, inexpensive debugging
interface that allows external access to the processor's internal registers and to mem-
ory/peripherals. OnCE capabilities are controlled through a serial interface, mapped
onto a JTAG test access port (TAP) protocol. Figure 16-1 shows the components of
the OnCE circuitry.
IDR
DBGACK
DBGRQ
BRKRQ
Pipeline
Information
.
ADDR
.
ATTR
PSTAT
PC
FIFO
DEBUG
The interface to the OnCE controller and its resources is based on the TAP defined
for JTAG in the IEEE-1149.1a-1993 standard.
16.2 Operation
An instruction is scanned into the OnCE module through the serial interface and then
decoded. Data may then be scanned in and used to update a register or resource on
a write to the resource, or data associated with a resource may be scanned out for a
read of the resource.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
SECTION 16
OnCE™ DEBUG MODULE
Breakpoint
Comparators
Figure 16-1 OnCE Block Diagram
OnCE™ DEBUG MODULE
For More Information On This Product,
Go to: www.freescale.com
Breakpoint and
Trace Logic
.
OnCE
Controller
and
Serial
Interface
Registers
and
TCK
TDI
TMS
TDO
TRST
DE
MOTOROLA
16-1
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