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16.9.1 Trace Counter (OTC) ................................................................................ 16-15
16.9.2 Trace Operation ........................................................................................ 16-15
16.10 Methods of Entering Debug Mode ............................................................... 16-16
16.10.1 Debug Request During RESET ................................................................. 16-16
16.10.2 Debug Request During Normal Activity..................................................... 16-16
16.10.3 Debug Request During Stop, Doze, or Wait Mode.................................... 16-16
16.10.4 Software Request During Normal Activity ................................................. 16-16
16.10.5 Enabling OnCE Trace Mode ..................................................................... 16-16
16.10.6 Enabling OnCE Memory Breakpoints........................................................ 16-17
16.11 Pipeline Information and Write-Back Bus Register ...................................... 16-17
16.11.1 Program Counter Register (PC) ................................................................ 16-18
16.11.2 Instruction Register (IR) ............................................................................ 16-18
16.11.3 Control State Register (CTL)..................................................................... 16-18
16.11.4 Write-Back Bus Register (WBBR) ............................................................. 16-19
16.11.5 Processor Status Register (PSR).............................................................. 16-19
16.12 Instruction Address FIFO Buffer (PC FIFO) ................................................. 16-20
16.13 Serial Protocol Description........................................................................... 16-21
16.13.1 OnCE Commands ..................................................................................... 16-21
16.14 Target Site Debug System Requirements.................................................... 16-21
16.15 Interface Connector For JTAG/OnCE Serial Port ........................................ 16-22
A.1
Maximum Ratings ............................................................................................A-1
A.2
DC Electrical Specifications .............................................................................A-1
A.3
Clock Input Specifications ................................................................................A-2
A.4
AC Electrical Specifications .............................................................................A-2
A.4.1
Reset, MOD Timing Specifications ..............................................................A-2
A.4.2
External Interrupt Timing Specifications ......................................................A-3
A.4.3
EIM Timing Specifications ...........................................................................A-4
A.4.4
ISPI Timing Specifications ...........................................................................A-6
A.4.5
OnCE Timing Specifications ........................................................................A-9
B.1
Overview ..........................................................................................................B-1
C.1
Peripheral Module Address Assignment ..........................................................C-1
C.2
Interrupt Controller Programming Model..........................................................C-2
C.2.1
Interrupt Source Register (INTSRC)............................................................C-2
C.2.2
Normal Interrupt Enable Register (NIER) ....................................................C-2
MOTOROLA
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Freescale Semiconductor, Inc.
TABLE OF CONTENTS
Title
APPENDIX B
PACKAGING AND PIN ASSIGNMENTS
For More Information On This Product,
Go to: www.freescale.com
Page
MMC2001
REFERENCE MANUAL
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