Ispi Operation In Low-Power System Modes; Ispi Operation In System Debug Mode - Motorola M-CORE MMC2001 Series Reference Manual

12.6 ISPI Operation in Low-Power System Modes

The following table summarizes ISPI operation in the different low-power modes.
In most modes, the ISPI operates as long as a clock is available. In doze mode, the
ISPI may be selectively disabled, depending on the value of the DOZE bit. In stop
mode, the ISPI halts immediately (due to halting of system clocks) and forgets the
state of any transfer in operation (the state machine is reset, and the shift register is
cleared). This is done to prevent hanging a transfer in the middle; it is assumed that
when stop is initiated, there is some other method of shutting down external devices.
The SPDR value is retained so that the transfer can be re-initiated after the system is
restarted by simply writing the SPI control register.

12.7 ISPI Operation in System Debug Mode

In debug mode, the only modification to ISPI behavior is that the clear-on-access
function of the IRQ bit in the SPI status register is disabled. Normally the IRQ bit is
cleared on a read or write access to the SPDR.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table 12-4 ISPI Low-Power Mode Operation
State
Normal Runs whenever enabled
Wait Runs whenever enabled
Doze If DOZE is set (in SPCR), then disabled
Stop
INTERVAL MODE SERIAL PERIPHERAL INTERFACE
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Operation
Disabled
MOTOROLA
12-11