Table of Contents
Advertisement
CLOCK COUNT
These bits select the length of the transfer and control the justification of data. From
two to 16 bits can be transferred. A count of all zeros causes the ISPI to be disabled.
C.8.3 ISPI Interval Control Register
The ISPI interval control register (SPICR) controls interval mode operation.
SPICR — ISPI Interval Control Register
15
14
13
12
R
0
IVL_
LPBK
EN
W
RESET:
0
0
0
0
LPBK — Loopback
This bit enables a loopback test feature in the ISPI. When looping back, the ISPI
operates as if the SPI_MISO and SPI_MOSI pins are wired together and there are no
other external devices connected to the ISPI data input pin. Whenever loopback is
enabled, the data read from the ISPI data register after a given transfer matches what
was written to the ISPI data register prior to that transfer, masked if necessary to
account for the number of bits transferred.
0 = Loopback disabled
1 = Loopback enabled
IVL_EN — Interval Mode Enable
This bit, when set, places the ISPI in interval mode. If the MSTR bit in the ISPI control
register is cleared, then the ISPI is operating in slave mode, and this bit is ignored.
0 = ISPI is not operating in interval mode
1 = ISPI is operating in interval mode if MSTR=1
INTERVAL COUNT
In interval mode, this register value is loaded into the ISPI interval timer upon comple-
tion of a transfer. Each bit-clock period, the value in this counter is decremented by
one. When the value in the register reaches zero, then XCH is set, and a new transfer
is begun.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
Table C-16 CLOCK COUNT Values
Value
0000
0001
.
.
0111
.
.
1111
11
10
9
8
0
0
0
0
Figure C-34 ISPI Interval Control Register
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
Meaning
Disable ISPI
2-bit transfer
.
.
8-bit transfer
.
.
16-bit transfer
7
6
5
4
INTERVAL COUNT
0
0
0
0
10008004
3
2
1
0
0
0
0
0
MOTOROLA
C-33
Advertisement
Table of Contents
