Pwm Period Register; Pwm Period Registers; Clk Sel Field Settings - Motorola M-CORE MMC2001 Series Reference Manual

1 = PWM is enabled and begins a new period. The following events occur:
The output pin changes state to start a new period (if width != 0 and
period != 0 and width < period)
The counter is released and begins counting
The comparators are enabled
The PWM IRQ bit is set, indicating the start of a new period if IRQ EN is set.
CLK SEL — Clock Select
These bits select the output of the divider chain.

15.2.2 PWM Period Register

The PWM period register (PWMPR) controls the period of the PWM by defining the
number of PCLKs in the period. When the counter value matches the value in this
register, an interrupt is posted and the counter is reset to start another period.
PWMPR0 — PWM0 Period Register
PWMPR1 — PWM1 Period Register
PWMPR2 — PWM2 Period Register
PWMPR3 — PWM3 Period Register
PWMPR4 — PWM4 Period Register
PWMPR5 — PWM5 Period Register
15 14 13 12
R 0 0 0 0
W
RESET:
PERIOD — Pulse Period
This is the value that causes the counter to be reset. There is one special case. When
PERIOD = 0, the output is never set high (0% duty cycle). In this case, the compara-
tor is loaded and the counter reset on every PCLK. In addition, if enabled, an interrupt
request is generated on every PCLK.
MOTOROLA
15-6
Freescale Semiconductor, Inc.
Table 15-2 CLK SEL Field Settings
Value
000
001
010
011
100
101
110
111
11 10 9 8
0 0
0 0
Figure 15-5 PWM Period Registers
PULSE WIDTH MODULATOR
For More Information On This Product,
Go to: www.freescale.com
Divide By
4
8
16
64
256
2048
16384
65536
7 6 5 4
PERIOD
0 0 0 0
10005002
1000500A
10005012
1000501A
10005022
1000502A
3 2 1 0
0 0 0 0
MMC2001
REFERENCE MANUAL