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start bit has been found, the data bits, parity bit (if parity is enabled), and stop bits are
shifted in. If parity is enabled, it is checked and its status is reported in the RX regis-
ter. Similarly, frame errors and breaks are checked and reported. When a new char-
acter is ready to be read by the host, RX READY is asserted and an interrupt is
posted (if enabled). If the receiver register is read as a 16-bit word, the interrupt is
automatically cleared and the data, along with four status bits, are read by the CPU.
CTS can be configured as an output to indicate a pending overrun.
Normal NRZ is expected when the infrared interface is disabled.
11.3.3 Infrared Interface
The infrared interface converts data to be transmitted or received as specified in the
IRDA Serial Infrared Physical Layer Specification.
For each zero to be transmitted, a narrow pulse which is 3/16 of a bit time is gener-
ated. For each one to be transmitted, no pulse is generated. External circuitry must
be provided to drive an infrared LED.
When the UART is receiving data, a narrow pulse is expected for each zero transmit-
ted, and no pulse is expected for each one transmitted. Circuitry external to the IC
transforms the infrared signal to an electrical signal.
11.3.4 16x Bit Clock Generator
The 16x bit clock generator provides the pre-scaled bit clocks to the transmitter and
receiver blocks. A divide ratio from one to 4096 may be selected in the UBRGR regis-
ter. The 16x bit clock generator provides sufficient flexibility to provide almost any
"standard" bit-clock from a variety of clock frequencies.
The baud rate error is computed as follows for 115.2 Kbps:
The input clock is
The divide ratio selected is
Actual baud rate:
Actual-required rates ratio:
This results in an error-per-bit ratio of 1.27%.
11.3.5 General UART Definitions
The following definitions apply to both the transmitter and receiver operation:
Bit Time — The time required to serially transmit or receive one bit of data.
Start Bit — One bit time of logic zero that indicates the beginning of a data frame. A
start bit must begin with a one-to-zero transition.
Stop Bit — One bit time of logic one that indicates the end of a data frame.
MOTOROLA
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
11-4
Freescale Semiconductor, Inc.
NOTE
For More Information On This Product,
Go to: www.freescale.com
16.38 Mhz
9 (UBRGR[11:0] = 8)
16.38 Mhz/9/16 = 113.75 khz
115.2/113.75 = 1.0127
REFERENCE MANUAL
MMC2001
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