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RXD Pin
Samples
1
1 1
RT CLK
(16X Bit Rate)
RT CLK
State
Reset RT
Figure 11-13 shows what occurs if noise causes a sample to be erroneously
detected as a zero before the actual beginning of the start bit. The logic zero sample
[1] in conjunction with the four preceding samples of logic one meet the conditions for
start qualification; thus, logic tentatively perceives the start bit as beginning here.
Subsequent start-verification samples at RT2, RT3, RT4, RT5, RT6, and RT7 [2] are
not all logic zeros; therefore, the tentative placement of the start edge is rejected, and
the search is restarted. When the sample at the actual beginning of the start bit is
detected, the preceding three samples are ones; the start bit is now perceived to
begin here. In this case, the three samples taken at RT2, RT3, RT4, RT5, RT6, and
RT7 [3] now verify that the start bit has been found. If the noise bit [1] is further away
from the beginning of the actual start bit, the perceived start bit will still be correct.
MOTOROLA
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
11-20
Freescale Semiconductor, Inc.
[1]
0
1
1
1
1
1
1
0 0
[2]
Figure 11-13 Start Bit — Noise Case One
For More Information On This Product,
Go to: www.freescale.com
Perceived Start Bit
Actual Start Bit
0
0
0 0
0
[3]
LSB
MMC2001
REFERENCE MANUAL
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