Once Controller - Motorola M-CORE MMC2001 Series Reference Manual

For accesses to the CPU internal state, the OnCE controller requests the CPU to
enter debug mode via the CPU DBGRQ input. Once CPU debug mode has been
entered, as indicated by the OnCE status register, the processor state may be
accessed through the CPU scan register.
The OnCE controller is implemented as a 16-state FSM, with a one-to-one corre-
spondence to the states defined for the JTAG TAP controller.
CPU registers and the contents of memory locations are accessed by scanning
instructions and data into and out of the CPU scan chain. Required data is accessed
by executing the scanned instructions. Memory locations may be read by scanning in
a load instruction to the CPU that references the desired memory location, executing
the load instruction, and then scanning out the result of the load. Other resources are
accessed in a similar manner.
Test-Logic-Reset
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Run-Test/Idle
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MOTOROLA
16-2
Freescale Semiconductor, Inc.
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Select DR-
Scan
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Capture - DR
Shift - DR
Exit1 - DR
Pause - DR
Exit2 - DR
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Update - DR
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Figure 16-2 OnCE Controller
OnCE™ DEBUG MODULE
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Go to: www.freescale.com
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Select - IR
Scan
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Capture - IR
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Shift - IR
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Exit1 - IR
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Pause - IR
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Exit2 - IR
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Update - IR
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MMC2001
REFERENCE MANUAL