Uart Port Data Register (Updr); Data Sampling Technique On The Receiver; Uart Port Data Register - Motorola Freescale Semiconductor M-Core MMC2001 Reference Manual

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PDCx — Port Direction Control Bit x
0 = Corresponding GPIO pin is configured as input
1 = Corresponding GPIO pin is configured as output
At reset, these bits are cleared to zero.

11.5.3 UART Port Data Register (UPDR)

The UART port data register is used to read or write data to or from UART GPIO pins.
U0PDR — UART0 Port Data Register
U1PDR — UART1 Port Data Register
15
14
13
12
R
0
0
0
0
W
RESET:
X = Undefined
PDx — Port Data Bit x
These bits are used to read or write data from/to the corresponding port pins if they
are configured as GPIO (by PC[3:0] bits in UPCR). If a port pin x is configured as a
GPIO input, then the corresponding PDx bit will reflect the value present on this pin. If
a port pin x is configured as a GPIO output, then the value written into the corre-
sponding PDx bit will be reflected on the pin.
Note that since the CTS and RTS pins are not present for UART1, the corresponding
port control register bits should be configured in a manner which provides determinis-
tic data when the port data register is read. One method for doing so is to configure
the missing pins as general-purpose outputs.

11.6 Data Sampling Technique on the Receiver

The UART receiver is responsible for synchronization to the serial data stream and
recovery of data characters. Since the data stream has no clock, data recovery
depends on the transmitting device and the receiving device operating at close to the
same bit rate. The UART system can tolerate a moderate amount of system noise
without losing any information.
The UART receive function is somewhat more difficult than the transmit function due
to the asynchronous nature of incoming serial data. A discussion of the way the
UART recognizes a start bit follows.
The receiver front-end logic uses a sampling clock that is 16 times the bit rate. This
sampling clock is called the RT clock in the following discussion, and one RT is under-
stood to be one-sixteenth of a bit-time. In the following figures, the RT clock cycles
are numbered from one (start of a bit time) to sixteen (end of a bit time).
MMC2001
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
11
10
9
8
0
0
0
0
Figure 11-11 UART Port Data Register
For More Information On This Product,
Go to: www.freescale.com
7
6
5
4
0
0
0
0
PD3
1000908E
1000A08E
3
2
1
0
PD2
PD1
PD0
X
X
X
X
MOTOROLA
11-17

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